The present invention relates to measuring the surface profile properties of features. The proposed metrology method compensates for phase changes associated with the presence of multiple or varying materials on the surface of a substrate and in particular, to a metrology method to measure dishing, erosion, and/or an actual height profile of features on a sample.
The metal interconnect of integrated circuits has conventionally been realized by blanket depositing a layer of metal on a planar insulating surface. Portions of the metal layer are subsequently removed in a photolithographically patterned etching step to form the resulting metal conductors. Conventional integrated circuits have generally employed somewhat resistive metal, such as aluminum, or metal alloys for the metal interconnect. Copper has been chosen as a replacement metal for aluminum in smaller geometry devices. Due to complexities associated with etching copper, it must be patterned in a different manner. Copper is blanket deposited over the wafer that has trenches and vias etched into the dielectric and then it is subjected to chemical mechanical polishing (CMP) to remove the copper from the upper planar surface. The goal is to have a globally planar surface composed of copper and dielectric regions.
FIGS. 1A through 1G show a cut-away view of the conventional fabrication of an aluminum interconnect. As shown in FIG. 1A, a relatively planar surface layer 10, which may be, e.g., a silicon substrate, is covered with a dielectric layer 12, e.g., an oxide layer, which is patterned and etched. An aluminum layer 14, which may be an aluminum alloy, is blanket deposited over the dielectric layer 12, as shown in FIG. 1B. A photoresist layer 16 is deposited over the aluminum layer 14 (FIG. 1C), and is exposed and developed resulting in the structure shown in FIG. 1D. The aluminum layer 14 is then etched, e.g., using a plasma etching technique, resulting in the structure shown in FIG. 1E. The remaining photoresist layer 16 is removed resulting in the structure shown in FIG. 1F. After these steps are completed, the surface is composed of metal lines with near vertical sidewalls above the surface of the dielectric layer 12, as shown in FIG. 1F. Subsequently, dielectric layers are deposited and etched over the metal lines to yield a dielectric layer 18 with a planarized surface, e.g., for the next metal layer, as shown in FIG. 1G.
A major change is being implemented in semiconductor processing by switching from aluminum to copper metallization. Copper is preferred to aluminum due to its lower resistivity and better electromigration resistance. Unfortunately, copper is difficult to etch and the switch from aluminum to copper has forced a change in the basic metallization process. Copper cannot simply be substituted for aluminum in the metallization process because plasma etching of copper is more difficult than plasma etching of aluminum (due to the lack of volatile copper halogen compounds). Additionally, if copper is allowed to directly contact the dielectric materials, it can rapidly diffuse through dielectric materials and contaminate the semiconductor devices.
Thus, a xe2x80x9cdamascenexe2x80x9d process has been developed whereby copper can be used as the interconnect metal. Rather than blanket depositing the interconnect metal on a substantially planar insulating substrate and then etching away parts of the metal layer to leave the conductors, trenches are formed in an insulating material. A composite layer of a diffusion barrier, nucleation layer and copper are then blanket deposited over the entire surface of the insulating substrate such that the trenches arc filled. Chemical mechanical polishing is then used to planarize the integrated circuit surface and thereby polish away all the metal that is not in the trenches. The result is metal conductors disposed in trenches and a globally planarized surface.
FIGS. 2A through 2C show a cut-away view of the conventional fabrication of a copper interconnect. As shown in FIG. 2A, a relatively planar surface layer 50, which may be, e.g., a silicon substrate, is covered with a dielectric layer 52, e.g., an oxide layer, which is patterned and etched. The dielectric layer 52 may be patterned and etched in multiple steps in order to produce trenches 54 and via 55. A diffusion barrier layer (not shown), nucleation layer (not shown), and copper layer 56 are blanket deposited over the dielectric layer 52 such that the trenches 54 and via 56 are filled, as shown in FIG. 2B. A chemical mechanical polishing step is then used to planarize the surface of the copper layer 56 (along with the diffusion barrier layer and nucleation layer) with dielectric layer 52, resulting in the structure shown in FIG. 2C.
The ideal copper CMP process removes the copper, nucleation layer and diffusion barrier from the surface of the dielectric while leaving behind the copper, nucleation layer and diffusion barrier in the trenches and contacts or vias. The ideal result would be a globally planarized surface with no vertical height change over the entire wafer surface. FIG. 3 shows the ideal resulting structure with a planar surface composed of a dielectric region 52 and idealized copper region 56. Global planarity is desirable because of the depth of field requirements associated with the lithographic steps. Significant height variations on the surface will compromise the photoresist processing steps and subsequently the etching and metallization processes. Height variations are also symptomatic of undesirable variations in the copper thickness and metal line resistance.
Unfortunately, because of the complexities associated with the CMP process, global planarity is not achievable. An artifact of the CMP processes in copper metallization results from the copper and dielectric material having different polishing rates, resulting in what is known as xe2x80x9cdishing.xe2x80x9d FIG. 4 shows a cut-away side view of the typical resulting structure after the CMP process, in which the surface of the copper region 56a is lower than the surrounding dielectric region 52a. It should be understood that FIG. 4 is for exemplary purposes and is not to scale. Dishing may generally be defined as the maximum height difference between the metal region 56a and the adjacent dielectric region 52a after CMP processing.
Another artifact caused by the CMP process, as known to those of ordinary skill in the art, is xe2x80x9cdielectric erosion,xe2x80x9d i.e., the dielectric regions exhibit a change in height over the surface of the wafer. This variation is related to the local density of metal features. Areas containing no metal features exhibit the highest dielectric surfaces, areas of low metal density exhibit relatively high dielectric surface regions and areas of high metal density result in relatively low dielectric surface regions.
The processing of silicon wafers to form integrated circuit chips requires many complex processing steps, for example, those described above. Each step must be carefully monitored and controlled to maximize the quality and yield of the final product. With the imminent replacement of aluminum by copper to form the metallization layers on silicon wafers, new processes and metrology techniques must be developed and implemented to characterize the degree of surface planarization after the CMP step.
Accordingly, what is needed is an economical, reliable, rapid, precise and accurate metrology procedure that can characterize and control individual steps during processing of a sample and specifically that will can be used to measure dishing, erosion, curvature, and/or the actual height profile of features on the sample.
A profiling method, in accordance with the present invention, compensates for phase changes associated with the presence of multiple materials or materials, such as transparent or composite materials, having varying thickness in an area of a substrate to be measured. The phase profile of the area of interest is first measured, e.g., using a differential interferometer. If there is more than one material present, the constant material specific phase shift associated with an opaque material or the thickness dependent, material specific phase associated with a transparent or composite material at a single location are obtained. For each pair of materials hit by the reference and measurement spots, the difference in the phase values for the two materials is used to generate a phase correction factor for the appropriate fraction of the data. Next, the phase versus thickness relationship is generated for any transparent or composite materials over the thickness range of interest. The phase versus thickness relationship is used to convert the measured phase to actual thickness or height for the transparent or composite regions. The phase versus thickness relationship for an opaque material is constant, so no correction is required for opaque regions. When all of the data is appropriately corrected, the present invention advantageously generates an accurate thickness or height profile for regions on a sample that may include dishing, erosion or other surface features in the presence of more than one material or stack of transparent materials.